Performance-augmented CMOS using back-end uniaxial strain

In this paper we report the first detailed electrical characterization of uniaxially-strained fully-depleted silicon-on-insulator (FD-SOI) n and p-channel MOSFETs. Using the back-end approach, an in-plane, tensile strain was applied to the FD SOI MOSFETs after device manufacture. Dies were thinned to membrane dimensions and then affixed to curved substrates. The die transfer process minimizes edge effects and spurious membrane behavior.