A data oriented approach to the design of reconfigurable stream decoders

The implementation technologies for electronic devices are experiencing a shift towards the use of reconfigurable devices. These devices are widely appreciated, especially in the design of embedded devices, since they allow to significantly lower the non-recurrent engineering costs associated with the hardware implementation of functionalities. In addition to these advantages, reconfigurable devices offer the possibility of implementing extremely flexible systems that can adapt or augment their hardware resources at run-time. To enable the exploitation of this important feature a key point is to make the designers able to model and validate reconfigurable systems, and to assist them in the evaluation of different target reconfigurable architectures. In this paper we address the problems of modeling configurability for streaming data decoding systems at a high level of abstraction, and of the subsequent synthesis on a reconfigurable device. In particular, we define an abstraction of a generic reconfigurable architecture based on elementary modular cells (reconfigurable architecture description layer, or RADL). To model and validate reconfigurable behaviors we defined a formalism that is based on the object-oriented features of Java and on its possibility to vary the class pool at run-time. We then formally address the problem of synthesizing such a high-level model upon the reconfigurable architecture abstraction defined. In order to explore the effectiveness of the model, we implemented a single RADL cell prototype and evaluated area cost and reconfiguration times.