Newly designed isolated RESURF LDMOS transistor for 60 V BCD process provides 20 V vertical NPN transistor

RESURF LDMOS transistors are utilized in high side driver applications and other applications that mandate electrical isolation between source and substrate by using isolated RESURF technology. However, the BCD process using conventional isolated RESURF LDMOS structures cannot provide high efficiency vertical NPN transistors due to the dependence of the RESURF LDMOS BV/sub dss/ (source to drain breakdown voltage) upon the epi thickness. In this paper, we propose a new isolated RESURF LDMOS. With the use of n-well near the drain region, we can avoid electric field concentration below the drain region. P-well dose, p-well length and extended drain dose should be optimized to reduce surface field of the proposed isolated RESURF LDMOS regardless of epi thickness.