Title :
Design of Low-Power Memory-Efficient Viterbi Decoder
Author :
Chen, Lupin ; He, Jinjin ; Wang, Zhongfeng
Author_Institution :
School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331, USA, Email: lpchen@eecs.oregonstate.edu
Abstract :
This paper presents a new low-power memory-efficient trace-back (TB) scheme for high constraint length Viterbi decoder (VD). With the trace-back modifications and path merging techniques, up to 50% memory read operations in the survivor memory unit (SMU) can be reduced. The memory size of SMU can be reduced by 33% and the decoding latency can be reduced by 14%. The simulation results show that compared to the conventional TB scheme, the performance loss of this scheme is negligible.
Keywords :
Computer science; Convolutional codes; Delay; Digital communication; Helium; Maximum likelihood decoding; Merging; Performance loss; USA Councils; Viterbi algorithm;
Conference_Titel :
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location :
Shanghai, China
Print_ISBN :
978-1-4244-1222-8
Electronic_ISBN :
1520-6130
DOI :
10.1109/SIPS.2007.4387532
