DocumentCode
2188836
Title
Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection
Author
Lin, Su-Hon ; Sheu, Ming-hwa ; Wang, Kuang-Hui ; Zhu, Jun-Jie ; Chen, Si-Ying
Author_Institution
Graduate School of Engineering Science and Technology, National Yunlin University of Science & Technology, 123 University Road, Section 3, Douliou, Yunlin 64002, Taiwan, g9110807@yuntech.edu.tw
fYear
2007
fDate
17-19 Oct. 2007
Firstpage
142
Lastpage
145
Abstract
A novel Hybrid-Carry-Selection (HCS) approach used for deriving an efficient modulo 2n-1 addition is presented in this study. Its resulting adder architecture which is mainly built by modified carry look-ahead adder (MCLA), carry prediction unit and simple multiplexer (MUX) is simple and regular for all n values. For VLSI implementation based on 180nm standard-cell technology, the HCS-based modulo 2n-1 adder demonstrates the superiority in AreaxTime (AT) performance over those of the latest existing solutions. The layout area and clock rate for HCS-based 216-1 modular adder chip are 25709 um2 and 518MHz respectively.
Keywords
Adders; Arithmetic; Circuits; Clocks; Computer architecture; Cryptography; Design engineering; Fault tolerant systems; Multiplexing; Very large scale integration; Hybrid carry selection; VLSI design; architecture; modular adder;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location
Shanghai, China
ISSN
1520-6130
Print_ISBN
978-1-4244-1222-8
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2007.4387534
Filename
4387534
Link To Document