Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit

In this paper, a framework of designing a low-error signed fixed-width multiplier that receives two n-bits operands and generates an n-bits product is proposed. The proposed error compensation circuit not only leads signed fixed-width multipliers to very low maximum error, mean error and mean-square error but also can be easily constructed with a simple logic gate. Moreover, the proposed signed fixed-width multiplier is also applied to the inverse discrete cosine transform computation in JPEG image compression. Experimental results demonstrate that the proposed circuit not only improves the accurate performance but also significantly reduces the hardware complexity and power consumption when compared with the previous published compensation circuit.