DocumentCode
2189021
Title
A high-speed programmable FIR digital filter using switching arrays
Author
Hong, Kuk-Tae ; Yi, Sung-Dae ; Chung, Kang-Min
Author_Institution
Dept. of Electron. Eng., Sungkyunkwan Univ., Kyungki, South Korea
fYear
1996
fDate
18-21 Nov 1996
Firstpage
492
Lastpage
495
Abstract
In this paper, we propose a programmable tap structure used in a programmable FIR digital filter for high-frequency communication system, which speed performance is comparable to the case of a non-programmable filter. A fully parallel bit-level pipelined transposed-form carry-save architecture using CSD coefficients was used to achieve high-sample rate FIR digital filter. For realization of programmable filter coefficients, two decoders and some registers were added, and these registered data controlled the shifting process of input data using switch arrays
Keywords
FIR filters; programmable filters; CSD coefficient; decoder; high-frequency communication system; high-speed programmable FIR digital filter; parallel bit-level pipelined transposed-form carry-save architecture; register; sample rate; switching array; tap structure; Decoding; Degradation; Delay; Digital filters; Educational institutions; Electronic mail; Finite impulse response filter; Frequency response; Pipeline processing; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-3702-6
Type
conf
DOI
10.1109/APCAS.1996.569321
Filename
569321
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