Graph-based quantum integrated circuits using III-V mulch-branch nanowire networks and their nano-Schottky gate control

Beyond the scaling limit of Si CMOS LSls, one envisages nanoelectronics based on quantum devices. To realize quantum LSls (Q-LSIs), however, a novel architecture is required that is suitable to non-robust and charge-sensitive quantum devices which manipulate a single or a few electrons. The cascaded logic gate architecture in Si LSIs is utterly unsuitable. The purpose of this paper is to propose a graph-based Q-LSI architecture and to investigate its basic feasibility by forming of high-density GaAs-based and InP-based multi-branch nanowire networks and controlling them by nanometer-scale Schottky gates.