High Efficiency Synchronous DRAM Controller for H.264 HDTV Encoder

A high efficiency memory controller of Synchronous DRAM is proposed to improve memory bandwidth in H.264 HDTV encoder. The feature of SDRAM and memory access pattern of H. 264/AVC encoder is analyzed for suitable controller architecture designing. A new data arrangement in SDRAM has been used to improve bus efficiency by reducing the overhead cycle of page-activation. Experiment results show that the proposed architecture has improved 40% performance of SDRAM bus efficiency.