Enhancement-mode GaAs MESFET technology for low consumption power and low noise applications

Author

Nakajima, S. ; Matsuzaki, K.-I. ; Otobe, K. ; Nishizawa, H. ; Shiga, N.

Author_Institution

Optoelectron. R&D Labs., Sumitomo Electr. Ind. Ltd., Yokohama, Japan

fYear

1994

fDate

23-27 May 1994

Firstpage

1443

Abstract

Ion implanted enhancement-mode GaAs MESFETs with an advanced LDD structure have been developed. A manufacturable self-aligned process based on a dummy gate was used for the fabrication of 0.3 /spl mu/m gate device. At 1 mW operation, a noise figure (NF) of lower than 1.0 dB with an associated gain of higher than 9.0 dB was measured at 6 GHz. Furthermore, a standard deviation of NF as small as 0.05 dB at an average of 0.83 dB was obtained over a 3"/spl Phi/ wafer.<>

Keywords

III-V semiconductors; S-parameters; Schottky gate field effect transistors; gallium arsenide; ion implantation; semiconductor device noise; semiconductor technology; solid-state microwave devices; 0.3 micron; 1 mW; 1.0 dB; 3 in; 6 GHz; 9.0 dB; GaAs; LDD structure; S parameters; dummy gate; fabrication; gain; ion implanted enhancement-mode GaAs MESFETs; noise figure; power consumption; self-aligned process; Fabrication; Gain measurement; Gallium arsenide; MESFETs; Manufacturing processes; Noise figure; Noise measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 1994., IEEE MTT-S International

Conference_Location

San Diego, CA, USA

ISSN

0149-645X

Print_ISBN

0-7803-1778-5

Type

conf

DOI

10.1109/MWSYM.1994.335140

Filename

335140