DocumentCode :
2190110
Title :
Rapid Abstract Control Model for Signal Processing Implementation
Author :
Gaddam, Kannan ; Chandrachoodan, Nitin ; Srinivasan, S.
Author_Institution :
IIT Madras, HCL Technologies Ltd, kannan.gaddam@hcl.in
fYear :
2007
fDate :
17-19 Oct. 2007
Firstpage :
418
Lastpage :
423
Abstract :
Evaluating different architectures is an important step in implementing signal processing algorithms in hardware. Often specific resource or memory requirements and performance can be estimated only through simulation. This can be difficult when detailed system descriptions are used. There is a need for quick simulation and estimation of performance. The Rapid Abstract Control (RAC) model is presented as an approach to solve this problem. Simple primitives are defined that can be used to construct models for simulation. The Single Scale Retinex (SSR) algorithm is used to demonstrate the effectiveness of the modeling approach.
Keywords :
Computational modeling; Computer architecture; Counting circuits; Field programmable gate arrays; Hardware; Logic; Signal processing; Signal processing algorithms; Throughput; Timing; Architecture; Data Flow Analysis; Design Automation; Field Programmable Gate Arrays; Image Processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location :
Shanghai, China
ISSN :
1520-6130
Print_ISBN :
978-1-4244-1222-8
Electronic_ISBN :
1520-6130
Type :
conf
DOI :
10.1109/SIPS.2007.4387584
Filename :
4387584
Link To Document :
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