Title :
Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension
Author :
Chen, Yu-Jen ; Chen, Yi-Hau ; Chuang, Tzu-Der ; Li, Chung-Te ; Chien, Shao-Yi ; Chen, Liang-Gee
Author_Institution :
National Taiwan University, Graduate Institute of Electronics Engineering, No. 1, Sec. 4, Roosevelt Road, Taipei, 10617 Taiwan, yjchen@video.ee.ntu.edu.tw
Abstract :
In addition to coding efficiency, the scalable extension of H.264/AVC provides good functionality for the adaptation in heterogeneous environments. Fine grain scalability (FGS) is a technique to extract video at the best quality level under the available bandwidth. In this paper, an architecture of FGS encoder with low external memory bandwidth and low hardware costs is developed. At most 92% bandwidth reduction can be attained by the proposed scan bucket algorithm, early context modeling with context reduction, and first scan pre-encoding. The area-efficient architecture is implemented by layer-wise hardware reuse, and three design strategies for enhancement layer coder are explored so that the trade-off between external memory bandwidth and silicon area is allowed. This design can real-time encode HDTV 1280Ã720 video at 130 MHz working frequency.
Keywords :
Arithmetic; Automatic voltage control; Bandwidth; Context modeling; HDTV; Hardware; Quadratic programming; Scalability; Streaming media; Video coding; CABAC; FGS; H.264/AVC scalable extension; SNR scalability; SVC; context-based adaptive binary arithmetic coding; fine grain scalability; scalable video coding;
Conference_Titel :
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location :
Shanghai, China
Print_ISBN :
978-1-4244-1222-8
Electronic_ISBN :
1520-6130
DOI :
10.1109/SIPS.2007.4387601