Ultrathin high-/spl kappa/ gate dielectric technology for germanium MOS applications

Author

Chi On Chui ; Ramanathan, S. ; Triplett, B.B. ; McIntyre, P.C. ; Saraswat, K.C.

Author_Institution

Dept. of Electr. Eng., Stanford Univ., CA, USA

fYear

2002

fDate

24-26 June 2002

Firstpage

191

Lastpage

192

Abstract

For the first time, we have successfully demonstrated the use of a high-/spl kappa/ gate dielectric material, ZrO/sub 2/, for CMOS applications on a pure germanium substrate. Using a low-temperature formation technique, we achieved excellent C-V characteristics with hysteresis of 1.5 mV and a capacitance-based equivalent SiO/sub 2/ thickness (t/sub ox,eq/) of about 5 /spl Aring/. Additionally, excellent device uniformity and very high device yield were attained.

Keywords

CMOS integrated circuits; capacitance; dielectric hysteresis; dielectric thin films; elemental semiconductors; germanium; integrated circuit yield; permittivity; zirconium compounds; 5 angstrom; C-V characteristics; CMOS applications; Ge; ZrO/sub 2/ high-/spl kappa/ gate dielectric material; ZrO/sub 2/-Ge; capacitance-based equivalent SiO/sub 2/ thickness; device uniformity; device yield; germanium MOS applications; germanium substrate; low-temperature formation technique; ultrathin high-/spl kappa/ gate dielectric technology; Capacitance; Capacitance-voltage characteristics; Dielectric substrates; Frequency; Germanium; High K dielectric materials; High-K gate dielectrics; Hysteresis; MOS devices; Surface treatment;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference, 2002. 60th DRC. Conference Digest

Conference_Location

Santa Barbara, CA, USA

Print_ISBN

0-7803-7317-0

Type

conf

DOI

10.1109/DRC.2002.1029595

Filename

1029595