Title :
A high throughput variable length decoder with modified memory based architecture
Author :
Shieh, Bui-Jue ; Lee, Yew-Sun ; Lee, Clierz Yi
Author_Institution :
Inst. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
31 May-3 Jun 1998
Abstract :
Variable-length code (VLC) is the most popular data compression technique. Therefore, a high throughput variable-length decoder (VLD) is required in many applications. In this paper, we propose two simple modified methods which can increase throughput of memory-based two-bit structure variable-length decoder system. The additional hardware of the modified architecture is a control unit and some memory space. The overall system still consists of control unit, arithmetic unit and memory. Simulation results show that the decompression rate based on 0.6 um CMOS process and MPEG2 coding table-15 can achieve 720 M bits/s with 100 MHz clock rate
Keywords :
CMOS digital integrated circuits; data compression; decoding; digital arithmetic; image coding; 0.6 micron; 100 MHz; 720 Mbit/s; CMOS process; MPEG2 coding; arithmetic unit; control unit; data compression technique; decompression rate; modified memory based architecture; throughput; two-bit structure; variable length decoder; Arithmetic; CMOS process; Clocks; Control systems; Data compression; Decoding; Hardware; Lab-on-a-chip; Memory architecture; Throughput;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706982
