DocumentCode
2190862
Title
Fast EBCOT Encoder Architecture for JPEG 2000
Author
Rathi, Somya ; Wang, Zhongfeng
Author_Institution
School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331, USA, Email: rathi@eecs.oregonstate.edu
fYear
2007
fDate
17-19 Oct. 2007
Firstpage
595
Lastpage
599
Abstract
Embedded Block Coding with optimized Truncation (EBCOT) is a very computation and hardware intensive algorithm. It consumes more than 50 percent processing time of JPEG2000 encoding system. In this paper, we present a new algorithm and architecture of Block Coder based on serial mode in JPEG2000. It processes two bit planes simultaneously along with the encoding of four bits of a stripe concurrently. The architecture is capable of encoding in the causal mode of the standard. The paper also describes a variant of pass switching arithmetic encoder which further reduces the computation time of tier 1 with minimal increase in hardware. The proposed architecture not only saves memory by 4K bits but also significantly increases the throughput. It is estimated that the throughput can be increased by over 50%. In addition, the new architecture also reduces memory access.
Keywords
Arithmetic; Block codes; Clocks; Computer architecture; Discrete wavelet transforms; Hardware; Image coding; Throughput; Transform coding; Very large scale integration; EBCOT-Tier 1; JPEG2000; VLSI; image compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location
Shanghai, China
ISSN
1520-6130
Print_ISBN
978-1-4244-1222-8
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2007.4387616
Filename
4387616
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