A power and resolution adaptive flash analog-to-digital converter

Author

Yoo, Jincheol ; Lee, Daegyu ; Choi, Kyusun ; Kim, Jongsoo

Author_Institution

Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

fYear

2002

fDate

2002

Firstpage

233

Lastpage

236

Abstract

A new power and resolution adaptive flash ADC, named PRA-ADC, is proposed. The PRA-ADC enables exponential power reduction with linear resolution reduction. Unused parallel voltage comparators are switched to standby mode. The voltage comparators consume only the leakage power during the standby mode. The PRA-ADC, capable of operating at 5-bit, 6-bit, 7-bit, and 8-bit precision, dissipates 69 mW at 5-bit and 435 mW at 8-bit. The PRA-ADC was designed and simulated with 0.18 μm CMOS technology. The PRA-ADC design is applicable to RF portable communication devices, allowing tighter management of power and efficiency.

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit simulation; high-speed integrated circuits; integrated circuit layout; low-power electronics; 0.18 micron; 435 mW; 69 mW; CMOS technology design; PRA-ADC; RF portable communication devices; exponential power reduction; flash ADC; layout; leakage power consumption; linear resolution reduction; power adaptive flash analog-to-digital converter; power dissipation; power management; resolution adaptive flash analog-to-digital converter; standby mode; threshold inverter quantization; unused parallel voltage comparators; Analog-digital conversion; CMOS technology; Circuits; Energy consumption; Inverters; Permission; Quantization; Radio frequency; Signal resolution; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on

Print_ISBN

1-5811-3475-4

Type

conf

DOI

10.1109/LPE.2002.146744

Filename

1029610