A methodology for modeling lateral parasitic transistors in smart power ICs

Switching of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and injects minority carriers into the substrate, which can affect the functionality of the chip. In order to evaluate protection measures, these parasitic transistors have to be included into a post layout simulation. In this paper, we present a methodology for automatically generating Verilog-A models for these parasites from layout data. As these models have to account for high injection effects and a distributed current flow, the convergence behavior of this models will be worse than that of classical bipolar models. We found a reasonable trade-off between convergence behavior and accuracy of the model.