Title :
A Cordic-Based Reconfigrable Systolic Array Processor for MIMO-OFDM Wireless Communications
Author :
Seki, Katsutoshi ; Kobori, Tomoyoshi ; Okello, James ; Ikekawa, Masao
Author_Institution :
System IP Core Research Laboratories, NEC Corp., Kawasaki, Japan, E-mail: k-seki@ap.jp.nec.com
Abstract :
A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed for MIMO-OFDM baseband processing. With CORDIC, the processor provides high computation efficiency, and a multi-thread interleaving architecture offers the advantage of a simple data transfer mechanism. Also presented are an array mapping method for calculating MMSE filter coefficients and a comparison of the processor´s performance with that of dedicated hardware. Despite its flexibility, the processor achieves a computational density of 57% that of dedicated hardware.
Keywords :
Arithmetic; Baseband; Computer architecture; Hardware; Interleaved codes; Iterative algorithms; MIMO; Phased arrays; Systolic arrays; Wireless communication;
Conference_Titel :
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location :
Shanghai, China
Print_ISBN :
978-1-4244-1222-8
Electronic_ISBN :
1520-6130
DOI :
10.1109/SIPS.2007.4387624
