High performance and low power FIR filter design based on sharing multiplication

Author

Park, Jongsun ; Jeong, Woopyo ; Choo, Hunsoo ; Mahmoodi-Meimand, Hamid ; Wang, Yongtao ; Roy, Kaushik

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2002

fDate

2002

Firstpage

295

Lastpage

300

Abstract

We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 μm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on the Wallace tree multiplier.

Keywords

FIR filters; adders; carry logic; flip-flops; low-pass filters; low-power electronics; 0.25 micron; CCFF; CSHM; FIR filter design; carry select adder; computation re-use; computation sharing multiplier; conditional capture flip-flop; high performance FIR filter; low pass filter; low power FIR filter; vector-scalar products; Adders; Algorithm design and analysis; Circuits; Computer architecture; Digital signal processing; Filtering; Finite impulse response filter; Flip-flops; High performance computing; Power engineering computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on

Print_ISBN

1-5811-3475-4

Type

conf

DOI

10.1109/LPE.2002.146758

Filename

1029624