A multiple-rotating-clock-phase architecture for digital data recovery circuits using Verilog-A

This paper presents an oversampling data recovery (DR) architecture using Verilog-A that employs a novel multiple-rotating-clock-phase (MRCP) concept for its operation. The MRCP-DR architecture is a variant of the eye-tracking DR architecture. Multiple rotating clock phases, supplied by a delay-locked loop (DLL), establish a window for detecting data edges. As a result, the window width becomes robust against process, voltage and temperature (PVT) variations. The MRCP architecture is tolerant of jitter on the local, blind, free-running oscillator that operates at approximately the incoming data frequency. Behavioral blocks are described and functional simulations are presented using the Verilog-A/Spectre/Cadence platform. The Verilog-A test benches allow the designer to perform system-level what-if analyses and make area, power and performance estimates.