Adiabatic flip-flops based on CPAL with channel length bias

This paper focuses on leakage reduction of adiabatic sequential circuits by using the gate-length biasing techniques in nanometer CMOS process. All circuits are simulated using HSPICE, and the BSIM4 model is adopted to reflect the characteristics of the leakage currents. Taken as an example, total power consumptions of a traffic light controller based on two-phase CPAL (complementary pass-transistor adiabatic logic) have been investigated in different frequencies. Simulation results show that the gate-length biasing techniques for adiabatic flip-flops increases slightly the delay of the gates and dynamic power of the circuits, and thus the sizes of gate-length have to be carefully considered.