DocumentCode
2191456
Title
PENELOPE: a graph based logic simulator for MOS circuits
Author
Castagnolo, B. ; Corsi, F. ; Martino, S.
Author_Institution
Dept. of Electrotech. & Electron., Bari Univ., Italy
fYear
1988
fDate
7-9 June 1988
Firstpage
1365
Abstract
A logic simulation tool called PENELOPE (Petri net logic performance evaluator) with precise delay estimation capabilities is presented. The simulator, which is particularly intended for CMOS circuits, makes use of a description of the logic network in terms of a Petri-net-like graph which implements the truth table of each logic operator and also processes the property of describing the evolution of the signal transitions in the network. Comparisons are made with other known simulators, showing that the performances are quite interesting especially in view of the precise modelling of time delays in the network.<>
Keywords
MOS integrated circuits; graph theory; integrated logic circuits; logic CAD; MOS circuits; PENELOPE; Petri net logic performance evaluator; delay estimation capabilities; graph based logic simulator; logic network; logic simulation tool; precise modelling; signal transitions; truth table; Bars; CMOS logic circuits; Circuit simulation; Delay effects; Digital circuits; Logic circuits; Logic devices; Performance evaluation; Petri nets; Signal resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo, Finland
Type
conf
DOI
10.1109/ISCAS.1988.15182
Filename
15182
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