Hierarchical symbolic piecewise-linear circuit analysis

This paper presents a hierarchical transient analysis method for piecewise-linear (PWL) circuits suitable for early stage verification of analog and mixed-signal circuits. The new method is based on a novel parameterized modeling of PWL devices, which results in very compact circuit matrices compared to existing PWL simulation algorithms based on ideal diode models. The new PWL symbolic analysis features exact symbolic solution of linear systems via graph based hierarchical analysis technique and PWL modeling of nonlinear devices. The resulting parameterized PWL circuit equations are solved by a modified Katzenelson event-driven algorithm to obtain transient responses for all subcircuits based on the symbolic solutions. Since PWL components are modeled symbolically in the new method, symbolic solutions are built only once and used repeatedly throughout the entire simulation, which makes the new PWL simulation algorithm more efficient than the Newton-Raphson (NR) based numerical methods, which require solving of linear equations (LU decomposition) at every step in NR iterations. Experimental results on a number of analog circuits show that the proposed hierarchical method outperforms the commercial simulator, SIMetrix and the flat PWL simulator.