HDL design for high speed Multichannel rate PRBS -GPS SOC transceiver for data acquisition and tracking using satellites based ultra high speed GPS mobile phone computing system

The Aim is for HDL Design & Implementation of Multichannel frequency rate PRBS- GPS SOC Transceiver Design using VHDL & Verilog HDL. GPS SOC Transceiver contains Transmitter & Receiver and Transceiver SOC by Integration of Transmitter & Receiver. Transmitter Contains PRBS - Base Band Signal Navigation Data Generator with frequency of 50 Hz & Carrier Wave Generator with a frequency of 1.057 MHz and C(t) is Pseudo Random Code (C/A Code of Satellite is 1.023 MHz) . PRBS GPS Base Band Signal Generator & Carrier Wave Generator are XOR ed by using XOR Gate for generation of Digital Modulated Signal by Tapping Different Sequence Patterns 2e⁷−1,2e¹⁰−1,2e¹⁵−1,2e²³−1,2e³¹−1 etc as per CCITT - ITU Standards (O.150,O.151,O.152) for Identification of Property of PRBS Modulated Signal codes and the same signal codes received by using PRBS GPS Receiver System and compared with the Received signal codes delayed with Transmitted one, and if the result is ‘0’, no error in the received sequence. ‘1’ means error occurred in the received sequence. Speed of Transmission & Reception rate is in terms of Gbps/Tbps/Peta/Exa/Zetta Bits Per Second. Coding done by VHDL &/ Verilog HDL. Programming & Debugging Done by Xilinx ISE 9.2i Software Design Tool and Xilinx Spartan III FPGA Development Kit.