DocumentCode
2191624
Title
Comparison of a BSIM3V3 and EKV MOST model for a 0.5 um CMOS process and implications for analog circuit design
Author
Terry, S.C. ; Rochelle, J.M. ; Binkley, D.M. ; Blalock, B.J. ; Foty, D.P. ; Bucher, M.
Author_Institution
Tennessee Univ., Knoxville, TN, USA
Volume
1
fYear
2002
fDate
10-16 Nov. 2002
Firstpage
317
Abstract
A BSIM3V3 and EKV model for a standard 0.5 um CMOS process has been evaluated for analog applications. Critical small-signal parameters including output conductance and transconductance efficiency were simulated for devices with gate lengths ranging from 0.5 um to 33 um. In addition, the small-signal parameters were measured on test devices with similar dimensions. The results highlight the difficulty of obtaining a model that accurately predicts the operation of low voltage analog circuits.
Keywords
CMOS analogue integrated circuits; MOSFET; integrated circuit design; low-power electronics; semiconductor device models; 0.5 micron; BSIM3V3 model; CMOS low-voltage analog circuit design; EKV model; MOS transistor; output conductance; small-signal parameters; transconductance efficiency; Analog circuits; CMOS process; CMOS technology; Circuit simulation; Circuit synthesis; Low voltage; MOS devices; Semiconductor device modeling; Telephony; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Nuclear Science Symposium Conference Record, 2002 IEEE
Print_ISBN
0-7803-7636-6
Type
conf
DOI
10.1109/NSSMIC.2002.1239324
Filename
1239324
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