New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS)

We present here the use of the performance predicting ECAD system, which is called Layout-design-based Interconnect Structure Optimization System (LADINOS), for the optimization of multilayer interconnect structures. This system is intended to be used to redesign current ULSI data on possible interconnect structures in the future and to measure the performance of such redesigned ULSIs. Despite the fact that system procedures include chip-size prediction, timing-driven assignment of interconnects to layers, and RC extraction which takes coupling capacitance into account, these procedures are performed very fast. We also give an example of the optimization of multi-layer interconnect structures for use in 0.13 μm-generation ULSIs with Al-interconnects