Title :
A 30-V P-channel trench gated DMOSFET with 900 μΩ-cm2 specific on-resistance at 2.7 V
Author :
Williams, Richard K. ; Grabowski, Wayne ; Darwish, Mahmoud ; Yilmaz, Hamza ; Chang, Mike ; Owyang, King
Author_Institution :
Silconix, Santa Clara, CA, USA
Abstract :
A scaled-oxide low-threshold P-channel trench gated DMOS employing a 12 Mcell/in2. (2 Mcell/cm2) closed-cell design, 8-V gate rating and 30-V drain rating is described. Measured specific resistances of 900 μΩ-cm2 at VGS=2.7 V and 700 μΩ-cm2. At VGS=4.5 V represent the lowest RDSA values ever reported for a P-channel DMOS with a 37-V breakdown. The benefit of a 3X scaling of gate oxide thickness is shown by measurement, analytical and numerical modeling to produce a 1.6-V reduction in threshold, a 75% reduction in channel resistance and a 45% reduction in overall trench DMOS on-resistance at V GS=4.5 V. High density 30-V planar DMOS die resistance is shown to be 3.7X that of the scaled-oxide trench DMOS at VGS=4.5 V
Keywords :
electric breakdown; electric resistance; isolation technology; power MOSFET; semiconductor device models; 2.7 V; 30 V; 4.5 V; 8 V; P-channel trench gated DMOSFET; breakdown; channel resistance; closed-cell design; drain rating; gate oxide thickness; numerical modeling; overall trench DMOS on-resistance; planar DMOS die resistance; scaled-oxide low-threshold device; specific on-resistance; Analytical models; Batteries; Communication switching; Electric breakdown; Electrical resistance measurement; Immune system; MOSFETs; Numerical models; Switches; Threshold voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 1996. ISPSD '96 Proceedings., 8th International Symposium on
Conference_Location :
Maui, HI
Print_ISBN :
0-7803-3106-0
DOI :
10.1109/ISPSD.1996.509447
