VLSI CMOS fabrication modules combine with power device methods to produce 40 mΩ and 65 mΩ, 7 V logic level P-power FETs

Author

Efland, Taylor ; Skelton, Dale ; Keller, Steve ; Frank, Kathy ; Mai, Quang

Author_Institution

Comput. Peripheral & Custom Power, Texas Instrum. Inc., Dallas, TX, USA

fYear

1996

fDate

20-23 May 1996

Firstpage

71

Lastpage

74

Abstract

In this paper, results are discussed from work completed on logic level low voltage power PMOS switches. The devices were fabricated using base line 7 V rated PMOS from an existing scaleable technology and applying power device design techniques to the structure. The goals were to demonstrate area efficient high current low on resistance switches with fast switching and robust performance in an SO8 form factor. Device performance achieved was R_dscn=65 mΩ@V_gs=-5.0 V, I_ds=-6 A with UIS switching up to 40 A at V_dd=-6 V; this device is shown alongside an 80% shrunk version. A 40 mΩ @ V_gs=-5.0 V, I_ds=-12 A version was demonstrated and is also reported in this work. Competitive R_sp was characterized for both N and P channel 7 V rated devices

Keywords

CMOS integrated circuits; VLSI; field effect transistor switches; integrated circuit measurement; power MOSFET; 12 A; 40 mohm; 6 A; 65 mohm; 7 V; SO8 form factor; UIS switching; VLSI CMOS fabrication modules; current switching; logic level P-power FETs; low voltage power PMOS switches; on resistance; power device methods; unclamped inductive switching; CMOS logic circuits; CMOS process; Fabrication; Instruments; Logic devices; Low voltage; Packaging; Robustness; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1996. ISPSD '96 Proceedings., 8th International Symposium on

Conference_Location

Maui, HI

ISSN

1063-6854

Print_ISBN

0-7803-3106-0

Type

conf

DOI

10.1109/ISPSD.1996.509451

Filename

509451