DocumentCode :
2192549
Title :
Response Time Analysis of the Abort-and-Restart Model under Symmetric Multiprocessing
Author :
Ras, Jim ; Cheng, Albert M K
Author_Institution :
Dept. of Comput. Sci., Univ. of Houston, Houston, TX, USA
fYear :
2010
fDate :
June 29 2010-July 1 2010
Firstpage :
1954
Lastpage :
1961
Abstract :
The Priority-Based Functional Reactive Programming (P-FRP) paradigm, aims to improve the programming of embedded microcontrollers. The combination of purely functional programming and cleanly-abortable event handlers, communicating via transactional memory (TM), makes it possible to write programs as stateless collections of functions, thus making them amenable to proofs and type safety. P-FRP implements executions as function evaluations, therefore, there are no "incomplete" function evaluations, as in the case of a task\´s interruption. To use P-FRP in the SMP (Symmetric Multiprocessor) environment, we must first understand the response time of programs written in its anticipated multiprocessor extension. Therefore, the contribution of this paper is the response time analysis for the Abort-and-Restart (ANR) event handler semantics of P-FRP for SMP Real-Time systems. ANR is neither a synchronization protocol nor a true scheduling policy. Instead, it is a policy for running tasks where the most important task is scheduled first. Results are derived for both fixed-priority (i.e., Rate Monotonic) and dynamic-priority (i.e., Earliest Deadline First) scheduling. We can say that the Abort-and-Restart and the TM models are similar, but also distinct, thus allowing our results to be adaptable for the analysis of TM.
Keywords :
concurrency control; embedded systems; functional programming; microcontrollers; multiprocessing systems; scheduling; abort-and-restart model; cleanly abortable event handlers; dynamic priority scheduling; embedded microcontrollers; functional programming; priority based functional reactive programming; response time analysis; symmetric multiprocessing; transactional memory; Computational modeling; Instruction sets; Interference; Processor scheduling; Servers; Time factors; Upper bound;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on
Conference_Location :
Bradford
Print_ISBN :
978-1-4244-7547-6
Type :
conf
DOI :
10.1109/CIT.2010.332
Filename :
5577989
Link To Document :
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