Single mask metal-insulator-metal (MIM) capacitor with copper damascene metallization for sub-0.18 μm mixed mode signal and system-on-a-chip (SoC) applications

Author

Liu, Ruichen ; Lin, Cheng-Yih ; Harris, Edward ; Merchant, Sailesh ; Downey, Stephen W. ; Weber, Gary ; Ciampa, Nicholas A. ; Tai, Wai ; Lai, Warren Y C ; Morris, Mark D. ; Bower, J.Eric ; Miner, John F. ; Frackoviak, John ; Mansfield, William ; Barr, Dav

Author_Institution

Lucent Technol. Bell Labs., Murray Hill, NJ, USA

fYear

2000

fDate

2000

Firstpage

111

Lastpage

113

Abstract

A one-mask metal-insulator-metal (MIM) capacitor using damascene Ca as the bottom electrode has been developed. Using a PECVD SiN as both the capacitor dielectric and the diffusion barrier for Cu we have demonstrated for the first time, the achieving of low leakage, high linearity MIM capacitors directly on Cu. The leakage and breakdown characteristics of the MIM capacitor depend strongly on both the surface conditions of the damascened Cu and on the PECVD SiN. We found that multilayered SiN is superior than single layer SiN, and Cu CMP plays an important role. However, the inevitable dishing on large area capacitors during Cu CMP shows little impact on the electrical characteristics

Keywords

MIM devices; capacitors; copper; masks; metallisation; 0.18 micron; Cu; SiN; SiN PECVD film; chemical-mechanical polishing; copper damascene metallization; dielectric material; diffusion barrier; electrical breakdown; leakage current; mixed mode signal processing; single mask MIM capacitor; system-on-a-chip; Copper; Costs; Dielectrics; Electrodes; MIM capacitors; Metal-insulator structures; Metallization; Silicon compounds; System-on-a-chip; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International

Conference_Location

Burlingame, CA

Print_ISBN

0-7803-6327-2

Type

conf

DOI

10.1109/IITC.2000.854297

Filename

854297