High voltage LDMOS transistors in sub-micron SOI films

Author

Paul, A.K. ; Leung, Y.K. ; Plummer, J.D. ; Wong, S.S. ; Kuehne, S.C. ; Huang, V.S.K. ; Nguyen, C.T.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1996

fDate

20-23 May 1996

Firstpage

89

Lastpage

92

Abstract

Silicon-on-insulator (SOI) LDMOS transistors with a linearly graded doping profile in the drift region have been found to exhibit both low on-resistance and high breakdown voltage. High-side operation is a problem for devices built in very thin SOI layers due to pinch-off of the drift region. This is less of a problem for devices built in thicker SOI layers. Devices built in thicker SOI films also are more tolerant of manufacturing variations and offer more predictable behaviour. Non-uniform self-heating within the drift region has been measured for the first time. A breakdown voltage of 1020 V is reported for a LDMOS transistor made in a 0.15 μm SOI layer

Keywords

power MOSFET; silicon-on-insulator; 0.15 micron; 1020 V; breakdown voltage; drift region; high voltage LDMOS transistor; high-side operation; linearly graded doping profile; on-resistance; pinch-off; self-heating; submicron SOI film; Boron; Doping profiles; Implants; Length measurement; Manufacturing; Power transistors; Silicon on insulator technology; Substrates; Time measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1996. ISPSD '96 Proceedings., 8th International Symposium on

Conference_Location

Maui, HI

ISSN

1063-6854

Print_ISBN

0-7803-3106-0

Type

conf

DOI

10.1109/ISPSD.1996.509455

Filename

509455