Adaptive Router Architecture for Optimising Quality of Service in Networks-on-Chip

Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router. Implementation results show up to 50% in reducing power consumption and up to 5 times reduction of memory utilisation in router architectures when compared with a traditional router. Moreover, simulation results show its superiority in terms of quality of service.