Title :
Generic models for interconnect delay across arbitrary wire-tree networks
Author :
Bhavnagarwala, Azeez J. ; Kapoor, Ashok ; Meindl, James D.
Author_Institution :
Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
New, generic and compact closed-form expressions for distributed wire-tree delay dependence on input ramp time, tree topology and wire geometries are reported. In agreement to within 5% of HSPICE simulations, these expressions permit rapid, accurate and early estimates of interconnect delay as well as variations in interconnect delay due to variations in interconnect process parameters across arbitrary distributed wire-tree networks
Keywords :
SPICE; delays; integrated circuit interconnections; integrated circuit modelling; trees (mathematics); HSPICE simulation; generic model; interconnect delay distribution; wire tree network; Delay effects; Delay estimation; Geometry; Large scale integration; Logic; Network topology; Propagation delay; Taylor series; Time domain analysis; Wire;
Conference_Titel :
Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International
Conference_Location :
Burlingame, CA
Print_ISBN :
0-7803-6327-2
DOI :
10.1109/IITC.2000.854302
