DocumentCode :
2192724
Title :
Reconfigurable parallel architecture of high speed round robin arbiter
Author :
Paul, Arnab ; Khan, Mamdudul Haque ; Muktadir Rahman, M. ; Khan, Tanvir Zaman ; Podder, Prajoy ; Khan, Yeasir Akram
Author_Institution :
Department of ECE at Institute of Engineering & Management (IEM), Kolkata, India
fYear :
2015
fDate :
24-25 Jan. 2015
Firstpage :
1
Lastpage :
5
Abstract :
With a view to managing the increasing traffic in computer networks, round robin arbiter has been proposed to work with packet switching system to have increased speed in providing access and scheduling. Round robin arbiter is a doorway to a particular bus based on request along with equal priority and gives turns to devices connected to it in a cyclic order. Considering the rapid growth in computer networking and the emergence of computer automation which will need much more access to the existing limited resources, this paper emphasizes on designing a reconfigurable round robin arbiter over FPGA which takes parallel requests and processes them with high efficiency and less delay than existing designs. Proposed round robin arbiter encounters with 4 to 12 devices. Results show that with 200% increment in the number of connected devices, only 2.69% increment has been found in the delay. With less delay, proposed round robin arbiter exhibits high speed performance with higher traffic, which is a new feature in comparison with the existing designs.
Keywords :
Clocks; Computers; Delays; Field programmable gate arrays; Hardware design languages; Registers; Round robin; ASM; round-robin arbiter; turn hit; turn miss; verilog HDL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015 International Conference on
Conference_Location :
Visakhapatnam, India
Print_ISBN :
978-1-4799-7676-8
Type :
conf
DOI :
10.1109/EESCO.2015.7253744
Filename :
7253744
Link To Document :
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