• DocumentCode
    2192761
  • Title

    Design and characterization of shorted gate FinFET for low power circuits

  • Author

    Pathak, Kalpana ; Tholkappia Arasu, G.

  • Author_Institution
    Department of Electronics and Communication Engineering, AVS Engineering College, Military Road, Ammapet, Salem - 636003, TN, INDIA
  • fYear
    2015
  • fDate
    24-25 Jan. 2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper represents a comprehensive analysis of characteristics of shorted gate Fin Field Effect Transistor (FinFET). Multi-gate devices are more and more desired in high performance digital circuits and systems. These have added advantages of high speed, higher packaging density on chips, low power operations and reduced area on chips. Non planar Complementary Metal Oxide Semiconductor (CMOS) devices, such as FinFETs, are promising for 22 nm or smaller technology. The fabrication process of FinFETs is much similar to that of planar CMOS transistor. FinFETs are better on leakage current management, short channel effects and perform well at subthreshold region. These have smaller threshold leading to faster operation. A novel FinFET device is designed using Electronic Design Automation (EDA) tools and subsequently characterized for various performance variables in this paper.
  • Keywords
    FinFETs; Leakage currents; Logic gates; Power demand; Silicon; Threshold voltage; CMOS; FinFET; multi-gate device; semiconductor devices; silicon on insulaton; transistor;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015 International Conference on
  • Conference_Location
    Visakhapatnam, India
  • Print_ISBN
    978-1-4799-7676-8
  • Type

    conf

  • DOI
    10.1109/EESCO.2015.7253746
  • Filename
    7253746