A study on current handling capability of dual gate MOS thyristor (DGMOS)

Author

Otsuki, M. ; Kirisawa, M. ; Sakurai, K.

Author_Institution

Matsumoto Factory, Fuji Electr. Co. Ltd., Nagano, Japan

fYear

1996

fDate

20-23 May 1996

Firstpage

137

Lastpage

140

Abstract

This paper describes the experimental results of new Dual Gate MOS Thyristor (DGMOS), which can be fabricated with the same process technology as IGBT. In order to investigate the mechanism of turn-off failure in a large chip, which occurs lower current density compared with smaller chip, 9.0×7.2 mm 600 V-DGMOS with internal gate interconnection have been evaluated. The inhomogenious current distribution is the major reason of turn-off failure. In order to realize higher current handling capability, the formation of lower resistance gate interconnection is one of the key technologies as well as developing the new cell structure which has higher latch-up immunity

Keywords

MOS-controlled thyristors; 600 V; current density; current distribution; current handling; dual gate MOS thyristor; gate interconnection; latch-up; turn-off failure; Cathodes; Current density; Current distribution; Electrodes; Geometry; Insulated gate bipolar transistors; MOSFET circuits; Physics; Thyristors; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1996. ISPSD '96 Proceedings., 8th International Symposium on

Conference_Location

Maui, HI

ISSN

1063-6854

Print_ISBN

0-7803-3106-0

Type

conf

DOI

10.1109/ISPSD.1996.509466

Filename

509466