A 0.8 μm high voltage IC using newly designed 600 V lateral IGBT on thick buried-oxide SOI

Author

Watabe, Kiyoto ; Akiyama, Hajime ; Terashima, Tomohide ; Nobuto, Shinichi ; Yamawaki, Masao ; Hirao, Tadashi

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1996

fDate

20-23 May 1996

Firstpage

151

Lastpage

154

Abstract

We have demonstrated that the developed process has a breakdown voltage of higher than 600 V with use of thick buried-oxide and thin SOI. From both experiments and simulations, the cylindrical structure in the LIGBTs shows the best performance; it improves the latch-up tolerance without the increase of on-state voltage. Moreover, the process we have developed is completely compatible with an existing 5 V, 0.8 μm CMOS process

Keywords

CMOS analogue integrated circuits; buried layers; insulated gate bipolar transistors; power integrated circuits; silicon-on-insulator; 0.8 micron; 600 V; CMOS process; breakdown voltage; buried-oxide SOI; cylindrical structure; high voltage IC; latch-up; lateral IGBT; on-state voltage; Breakdown voltage; CMOS process; CMOS technology; Electrodes; Etching; Insulated gate bipolar transistors; Integrated circuit technology; Isolation technology; Laboratories; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1996. ISPSD '96 Proceedings., 8th International Symposium on

Conference_Location

Maui, HI

ISSN

1063-6854

Print_ISBN

0-7803-3106-0

Type

conf

DOI

10.1109/ISPSD.1996.509469

Filename

509469