• DocumentCode
    2193049
  • Title

    A low-latency adaptive asynchronous interconnection network using bi-modal router nodes

  • Author

    Gill, Gennette ; Attarde, Sumedh S. ; Lacourba, Geoffray ; Nowick, Steven M.

  • Author_Institution
    Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
  • fYear
    2011
  • fDate
    1-4 May 2011
  • Firstpage
    193
  • Lastpage
    200
  • Abstract
    A new bi-modal asynchronous arbitration node is introduced for use as a building block in an adaptive asynchronous interconnection network. The target network topology is a variant Mesh-of-Trees (MoT), combining a binary fan-out network (i.e. routing) and a binary fan-in network (i.e. arbitration) for each source-sink pair. The key feature of the new arbitration node is that it dynamically reconfigures based on the traffic it receives, entering a special “single-channel-bias” mode when the other channel has no recent activity. Arbitration is totally bypassed on the critical path, resulting in significantly lower node latency and, in high-traffic scenarios, improved throughput. The router nodes were implemented in IBM 90nm technology using ARM standard cells. SPICE simulations indicate that the bi-modal arbitration node provided significant reductions in latency (41.6%), and increased throughput (19.8%, in high-traffic single-channel scenarios), when in biased mode. Node reconfiguration required at most 338 ps. Simulations were then performed on two distinct MoT indirect networks, “baseline” and “adaptive” (the latter incorporating the new bi-modal node), on eight diverse synthetic benchmarks, using mixes of random and deterministic traffic. Improvements in system latency up to 19.8% and throughput up to 27.8% were obtained using the adaptive network. Overall end-to-end latencies, through 6 router nodes and 5 hops, of 1.8-2.8 ns (at 25% load) and throughputs of 0.27-1.8 Gigaflits/s (at saturation rate) were also observed.
  • Keywords
    SPICE; asynchronous circuits; circuit simulation; integrated circuit interconnections; logic design; network routing; network topology; ARM standard cell; IBM technology; MoT indirect network; SPICE simulation; bimodal asynchronous arbitration node; bimodal router node; binary fan-in network; binary fan-out network; end-to-end latency; high-traffic single-channel scenario; low-latency adaptive asynchronous interconnection network; lower node latency; mesh-of-trees; network routing; network throughput; network topology; single-channel-bias mode; size 90 nm; source-sink pair; system latency; Latches; Logic gates; Monitoring; Network topology; Routing; Safety; Throughput; B.4.3 [Hardware]: I/O and Data Communications—Interconnections (Subsystems)—Asynchronous operation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on
  • Conference_Location
    Pittsburgh, PA
  • Electronic_ISBN
    978-1-4503-0720-8
  • Type

    conf

  • Filename
    5948563