DocumentCode :
2193073
Title :
Optimizing the vertical IGBT structure-the NPT concept as the most economic and electrically ideal solution for a 1200 V-IGBT
Author :
Laska, T. ; Fugger, J. ; Hirler, F. ; Scholz, W.
Author_Institution :
Siemens AG, Munich, Germany
fYear :
1996
fDate :
20-23 May 1996
Firstpage :
169
Lastpage :
172
Abstract :
In this paper a new low loss 1200 V IGBT is discussed: optimizing the vertical structure of a fast switching IGBT in economic standard NPT-DMOS-technology, will result (without increase of switching losses) in a lowered on state voltage close to 2 V, a value which until now was believed to be reachable only by implementing problematic trench technology. Key points in this development are improvements in the ability of handling thin wafers below 200 μm as well as modifications of the backside p emitter
Keywords :
insulated gate bipolar transistors; losses; power semiconductor switches; power transistors; 1200 V; 2 V; 200 micron; NPT-DMOS-technology; backside p emitter modifications; fast switching IGBT; low loss IGBT; vertical IGBT structure; Charge carrier processes; Computer simulation; Current measurement; Energy measurement; Insulated gate bipolar transistors; Leakage current; Loss measurement; Power generation economics; Semiconductor device measurement; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and ICs, 1996. ISPSD '96 Proceedings., 8th International Symposium on
Conference_Location :
Maui, HI
ISSN :
1063-6854
Print_ISBN :
0-7803-3106-0
Type :
conf
DOI :
10.1109/ISPSD.1996.509473
Filename :
509473
Link To Document :
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