Title :
Hardware design for SHA-1 based on FPGA
Author :
Hua, Zhou ; Qiao, Liu
Author_Institution :
Dept. of Electron., Guizhou Univ., Guiyang, China
Abstract :
The SHA-1 algorithm in Hash Function was widely used in TPM hardware design. This paper proposes a design of SHA-1 hash function operations on FPGA hardware implementations. Optimized the structure of the module about the algorithm, which implement the simulation and synthesis. The frequency and resource used was satisfied with the TPM specification. Implement the modules use Hardware Design Language in RTL level, could generate in Soft-Core, which used in Trusted Computing hardware design.
Keywords :
field programmable gate arrays; FPGA hardware implementations; SHA-1 algorithm; hardware design; hardware design language; hash function; Algorithm design and analysis; Cryptography; Field programmable gate arrays; Hardware; Hardware design languages; Integrated circuit modeling; Software; FPGA; SHA-1; TPM;
Conference_Titel :
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location :
Ningbo
Print_ISBN :
978-1-4577-0320-1
DOI :
10.1109/ICECC.2011.6067630
