A flip-chip implementation of the Data Encryption Standard (DES)

We describe a flip-chip MCM-D implementation of a Data Encryption Standard (DES) engine. Novel features include the following: use of dense area-array I/O to achieve high bandwidth, fully-pipelined architecture which supports multiple encryptions (e.g., triple DES) with no loss of throughput; ability to multiplex datastreams, each under the control of a potentially unique key, and use of the MCM-D substrate to distribute power, ground and clock signals. The chip is being fabricated in a 0.6 μm CMOS process, while the MCM is being built in a 4-layer polyimide MCM-D process. Circuit simulations indicate the device will operate with a throughput of 9.6 Gb/s