A flexible H.263 video coder prototype based on FPGA

The methodology used for prototyping an H.263 video coder is explained in this paper. The coder is based on an architecture, we have called MVIP-2, which consists of a set of specialized processors for the main tasks (transforms, quantizers, motion estimation and motion compensation) and a RISC processor for the scheduling tasks. The design has been written in synthesizable Verilog and fully tested with hardware-software co-simulation using standard video sequences. All modules except the RISC has been synthesized and fitted onto an EP20K400BC652 FPGA from Altera. At present we are testing the prototype in real-time using a commercial board with the RISC and the FPGA, a pattern generator and data acquisition system to generate the input sequences and to read the reconstructed ones, as well as a logic analyzer. The methodological aspects presented in this paper can be applied to other designs.