DocumentCode :
2193704
Title :
A 7 level metallization with Cu damascene process using newly developed abrasive free polishing
Author :
Yamaguchi, H. ; Ohashi, N. ; Imai, T. ; Torii, K. ; Noguchi, J. ; Fujiwara, T. ; Saito, T. ; Owada, N. ; Homma, Y. ; Kondo, Satoshi ; Hinode, K.
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
fYear :
2000
fDate :
2000
Firstpage :
264
Lastpage :
266
Abstract :
A 7 level metallization including 4 levels of Cu metallization by the damascene technique is successfully developed using newly developed abrasive free polishing (AFP). This new AFP process reduced erosion and dishing, defect density, and improved TDDB lifetime of dielectric layers. We also improved corrosion resistance for Cu wiring. This process was used to fabricate a metallization structure of a new-cache memory chip consisting of 9-Mb 0.6-ns SRAMs and 200-K 25 ps ECL gate arrays. And this Cu metallization suppresses parasitic capacitance of interconnects and reduces clock wiring delay by 30%
Keywords :
copper; metallisation; polishing; Cu; ECL gate array; SRAM; TDDB lifetime; abrasive-free polishing; cache memory chip; clock wiring delay; copper interconnect; corrosion resistance; damascene process; defect density; dielectric layer; dishing; erosion; multilevel metallization; parasitic capacitance; Abrasives; Corrosion; Metallization; Page description languages; Plugs; Slurries; Sputtering; Tin; Tungsten; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International
Conference_Location :
Burlingame, CA
Print_ISBN :
0-7803-6327-2
Type :
conf
DOI :
10.1109/IITC.2000.854343
Filename :
854343
Link To Document :
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