An optimized integration scheme for 0.13 μm technology node dual-damascene Cu interconnect

Author

Lin, Shyue-Shyh ; Chen, Chih-Wei ; Huang, Shien-Ming ; Kang, Tsung-Kuei ; Yeh, Chen-Nan ; Li, Tsyr-Lih ; Tsui, Bing-Yue ; Hsia, Chin C.

Author_Institution

Deep Sub-Micron Technol. Div., ERSO/ITRI, Hsinchu, China

fYear

2000

fDate

2000

Firstpage

273

Lastpage

275

Abstract

From electrical simulations, the best performance dual damascene Cu/FSG integration scheme has been defined to be via first without etching stop layer and with thinnest possible sealing nitride layer. To realize this process, 0.16 μm and 0.27 μm (local and global interconnect) borderless via chains (100 K) with minimum 0.36 μm pitched metal lines (10 cm) were used as test vehicles. Sacrificial layer filled process was then defined with its process window carefully studied. From good electrical results with clearly defined process window, it is concluded that the proposed integration scheme is suitable for sub-0.13 μm technology node applications

Keywords

copper; integrated circuit interconnections; 0.13 micron; Cu; copper dual damascene interconnect; electrical simulation; etch stop layer; fluorosilicate glass; process integration; process window; sacrificial layer; sealing nitride layer; via first process; Capacitance; Dielectric films; Electrons; Etching; Plasma applications; Protection; Silicon compounds; Surface resistance; Testing; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International

Conference_Location

Burlingame, CA

Print_ISBN

0-7803-6327-2

Type

conf

DOI

10.1109/IITC.2000.854346

Filename

854346