A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit

It´s a promising way to improve performance significantly by adding reconfigurable processing unit to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. The Reconfigurable Logic is logically divided into Reconfigurable Processing Units (RPUs), which are coupled with General Purpose Cores (GPCs) as co-processors via a configurable full crossbar switch. And a RPU-Manager (RPU-M) is designed to manage the RPUs. To verify RMC, a simulation methodology based on the Simics and Virtex 5 FPGA is adopted, which simplifies the simulation and assures the accuracy of the hardware function core. The experimental results of workloads 3-DES, AES and JPEG_ENC show a 2.34X average speedup over software implementation, while the data and control transfer overhead is acceptable.