Title :
Defect-oriented analysis of memory BIST tests
Author_Institution :
HPL Inc., San Jose, CA, USA
Abstract :
This paper describes a defect-oriented analysis of 4 BIST tests that are used to test a commercial 6-port embedded SRAM. We examine the realistic fault and defect coverages of these memory BIST tests. We also uncover the subtle effect that addressing order has on the coverage that a test can provide. In addition, we show that the coverage that a test provides can vary from row to row depending on the addressing scheme.
Keywords :
built-in self test; design for testability; integrated circuit testing; integrated memory circuits; logic testing; storage allocation; DFT method; addressing order; commercial embedded SRAM; defect coverage; defect-oriented analysis; fault coverage; memory BIST tests; six-port embedded SRAM; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit faults; Clocks; Computational modeling; Power supplies; Random access memory; Read-write memory; Semiconductor device testing;
Conference_Titel :
Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on
Print_ISBN :
0-7695-1617-3
DOI :
10.1109/MTDT.2002.1029756
