DocumentCode :
2194296
Title :
Digital circuit crosstalk delay faults test generation based on neural networks
Author :
Jianshu, Zhang ; Xiuju, Zhang
Author_Institution :
Property Center of Logistics Group, Beihua Univ., Jilin, China
fYear :
2011
fDate :
9-11 Sept. 2011
Firstpage :
2628
Lastpage :
2631
Abstract :
Crosstalk faults arise easily between adjacent signal lines in integrated circuit. The faults make circuit´s output signal delay. This paper proposed an effective test generation algorithm for the crosstalk fault. Kernighan-Lin-Fiduccia-Mattheyses(KLFM) method is used to cut the circuit into two parts including the left and right parts. For the right part, the fault can be propagated to the output using neural networks method, the test patterns obtained by the method become a constraint condition; for the left part, a crosstalk fault equation can be obtained. The patterns that satisfy the constraint condition and make the delay equation have maximal value are the test generation patterns for the crosstalk fault. The experimental results demonstrate that the algorithm´s fault coverage can reach 96% and the algorithm´s test generation time is less than that of other references.
Keywords :
circuit testing; neural nets; Kernighan-Lin-Fiduccia-Mattheyses method; crosstalk fault equation; delay equation; digital circuit crosstalk delay faults test generation; effective test generation algorithm; integrated circuit; neural networks; test generation time; Algorithm design and analysis; Circuit faults; Crosstalk; Delay; Logic gates; Neural networks; Vectors; crosstalk fault; fault coverage; integrated circuit;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location :
Ningbo
Print_ISBN :
978-1-4577-0320-1
Type :
conf
DOI :
10.1109/ICECC.2011.6067669
Filename :
6067669
Link To Document :
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