A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

Author

Huang, Rei-Fu ; Li, Jin-Fu ; Yeh, Jen-Chieh ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2002

fDate

2002

Firstpage

68

Lastpage

73

Abstract

We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature - it can simulate the sequence of the detected faults in the real order, improving the accuracy of the analysis results.

Keywords

built-in self test; circuit simulation; digital simulation; fault simulation; integrated circuit reliability; integrated circuit testing; integrated memory circuits; random-access storage; redundancy; RAM; built-in redundancy analysis algorithms; built-in self-repair; detected faults sequence simulation; memory configuration; memory testing; redundancy analysis algorithms evaluation; redundancy structure; repair rate calculation; repairable embedded memories; simulator; Algorithm design and analysis; Analytical models; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Fault detection; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on

ISSN

1087-4852

Print_ISBN

0-7695-1617-3

Type

conf

DOI

10.1109/MTDT.2002.1029766

Filename

1029766