Title :
Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch
Author :
Gibbins, Robert ; Adams, R. Dean ; Eckenrode, Thomas ; Ouellette, Michael ; Wu, Yuejian
Author_Institution :
Nortel Networks, Ottawa, Ont., Canada
Abstract :
This paper presents the design, fault modeling, and BIST solution of an application specific 9-port SRAM. The use of the 9-port SRAM in place of more conventional memory in a 100 Gb/s SONET switch ASIC resulted in calculated reductions of 43% in die size, 31% in power consumption and 75% in data memory bit count. A custom programmable BIST solution was implemented that takes into consideration the memory´s special features such as the large number of ports, large read-to-write port asymmetry and the TDM read scheme.
Keywords :
SONET; SRAM chips; application specific integrated circuits; built-in self test; fault simulation; packet switching; 100 Gbit/s; 9-port SRAM; BIST solution; SONET; STS-1 switch; TDM read scheme; application specific IC; custom programmable solution; data memory bit count; die size; fault modeling; power consumption; read-to-write port asymmetry; Application specific integrated circuits; Built-in self-test; Decoding; Microelectronics; Random access memory; Read-write memory; SONET; Switches; Testing; Time division multiplexing;
Conference_Titel :
Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on
Print_ISBN :
0-7695-1617-3
DOI :
10.1109/MTDT.2002.1029767
