DocumentCode
2194383
Title
The realization of the Negative Logarithmic Function based on FPGA
Author
Wei-hua, Ruan
Author_Institution
Dept. of Electr. & Electron. Eng., Nanjing Inst. of Ind. Technol., Nanjing, China
fYear
2011
fDate
9-11 Sept. 2011
Firstpage
565
Lastpage
568
Abstract
This paper presents the realization of the Negative Logarithmic Function based on the FPGA chip EP2C5T144 by QuartusII software. It is designed a sequential circuit by the interpolation method and its´ fast clock frequency can arrive 400 MHz. It´s very good that the result of the hardware test by SignalTap II.
Keywords
field programmable gate arrays; sequential circuits; FPGA chip EP2C5T144; QuartusII software; fast clock frequency; interpolation method; negative logarithmic function; sequential circuit; Clocks; Cyclones; Digital signal processing; Field programmable gate arrays; Hardware; Sequential circuits; Software; FPGA; Hardware Test; NLF; Simulation; Synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location
Ningbo
Print_ISBN
978-1-4577-0320-1
Type
conf
DOI
10.1109/ICECC.2011.6067671
Filename
6067671
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